| Abstract |
Field-Programmable-Gate-Arrays (FPGAs) offer the promise of substantial
performance improvements over conventional processors by allowing the implementation of application-specific datapaths that exploit
instruction-level parallelism or domain-specific numeric formats and operations. Unfortunately FPGAs are still difficult to program making
them inaccessible to the average developer. The standard practice application program in a
hardware-oriented language such as Verilog or VHDL, and synthesize the hardware design using a variety of synthesis tools. Because of the
complexity of the synthesis process, it is difficult to predict a priori the performance and space characteristics of the resulting design. For
this reason, the developer usually engages in an iterative design process, examining the results, and modifying the design to trade off
performance for space.
In this presentation we describe DEFACTO, a system that automatically maps computations written in high-level imperative programming languages
such as C to multi-FPGA-based systems. DEFACTO combines parallelizing compiler technology with commercially available behavioral synthesis
tools. We use synthesis estimation techniques to guide the application of high-level program transformations in the search of high-quality hardware
designs, thereby avoiding the long compilation/synthesis design cycles. We illustrate the
effectiveness of DEFACTO in exploring a wide space of implementation designs for a set of image processing computations. For
these computations DEFACTO searches on average less than 0.3% of the design space while deriving an
"optimal" implementation, leading up to 4 orders of magnitude reduction in design time. We also describe in
detail the mapping of a digital image processing computation, the Sobel edge detection, for which DEFACTO yields a 60-fold reduction in design
time with only a 59% increase in execution time as compared to a manual implementation of the same algorithm.
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